The source files for Altera models are located in: altera/10.0/quartus/eda/sim_lib/. When installing or upgrading Modelsim, one has to recreate libraries as follows: The solution is add the following line to either modelsim.ini (or project.mpf): After contacting Mentor Graphics, it turns out that the path to some directories were previously hardcoded and not anymore. For simple stuff like a log2 function (common before the $clog2 function was added) you can safely `include inside your design unit (module, interface, etc).When loading my mpf file from older ModelSim revisions into v6.6c, any compile would fail with error message: Error: library std not found. Typing is a bit odd in SystemVerilog, so if you need to use a package across multiple files, import is the way to go to get consistent typing across modules. I haven't tried this style with packages but I don't see why it wouldn't work. Import TimerPackage::* parameter TimerAction P_TIMER_ACTION Old style ports: You can do something like this: I'm not sure if that that can precede a parameter list, but it can precede a port list. Import in module: SV-2009 allows you to import after the module name.Outside the module ($unit): If you import outside of a module/interface/class, you put the package in some semi-global space called $unit.NOTE: You must compile the package first! Explicit type: You can use TimerPackage::TimerAction as the parameter type.In SystemVerilog you can import packages in a few places. Doing `include will copy the content of the include file into the design unit you're compiling, hence the duplicate definition error. What I've had the most luck with is compiling the package on its own like you would a module rather than include. The auto generated modelsim script compiles it as needed.Īdmittedly, I only write SystemVerilog on and off, and I've had similar issues with packages.
QUARTUS CANNOT RUN MODELSIM ALTERA HOW TO
I could look into how to do that in SystemVerilog, however I'm now just wondering how this is normally done.Įdit: NVM not sure why but trying the packages/pkg_timer.sv method now works. This is similar to what happens in C / C++ if you include a file twice (from within the same file), to get around it you use: #ifndef _FILE_NAME_H This then fails in Quartus with "identifier TimerPackage" is already declared in the previous scope. įinally I tried changing my package file to timer.pkg and using a `include from the top of every file that needs that package definition. This of course fails as when it tries to compile a file that uses my package. However when I go to tools->run simulate tool->RTL simulation, Modelsim opens and tries to run: Test_run_msim_rtl_verilog.do which seems to be an auto generated script that compiles all my (non-testbench) files EXCEPT my package file, and then calls my msim_compile.do script. Vlog -sv -work work +incdir+PATH/packages I have Quartus set up to use a custom compile script for modelsim, which is called msim_compile.do and looks like. I then tried moving the package definition into another file packages/pkg_timer.sv, added that to my list of files at the top and all is great. package TimerPackage Īt first I had this at the top of my Timer.sv file, but then it only works if my files are compiled in the correct order, which with just one package is fine, I can just make sure Timer.sv is first in the list, but that sounds like bad practice. To allow passing this in from other modules I have the enum defined in a package. I want to use an enum here for clarity, so I can have ACTION_NONE and ACTION_TOGGLE. I'm working a module, one parameter is a single bit input.
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